With high definition TV (HDTV) broadcasts widely available and with the requirement of supporting standard definition TV (SDTV) as well as PC graphics, cost effective system-on-chip (SOC) HDTV/SDTV/Graphics solutions are very desirable. These SOCs require analog front end integration on the same die with a very large amount of digital circuitry. For example, a typical HDTV/SDTV/PC-graphic processor may integrate 3 ADC channels, multiple asynchronous phase-locked-loops (PLLs) and delay-locked-loops (DLLs), and 6 digital-to-analog converters (DACs) with a digital signal processing section of 8 million digital gates or more in a 90 nm or smaller digital CMOS process. An integrated circuit (IC) package with 544 pins or more may be required to implement such a processor due to such a large number of input/output pins. These packages may have a large inductance on analog power supply connections, thus creating additional internal power-supply noise. Also, with the competitive market in consumer electronics and high wafer costs in smaller geometry processes, any solution that will require large die-area, such as multi-stage active analog filters, is not very desirable. In addition, since analog video signals can be single-ended, meeting the noise requirements for an analog-to-digital converter (ADC) can be much more difficult.
A typical interface for an analog signal to an ADC is a sample-and-hold circuit. FIG. 1 demonstrates a typical sample-and-hold circuit 10. The sample-and-hold circuit 10 obtains samples of an input signal VIN at a given sampling rate, and provides discrete time output samples of the input signal VIN to a given ADC. The input signal VIN could be a differential signal. The sample-and-hold circuit 10 includes a sample stage 12 and a hold stage 14. The sample stage 12 could operate to obtain the samples of the differential signal VIN at a given sampling rate. The hold stage 14 could operate to transfer the obtained samples to an output of the sample-and-hold circuit 10 as discrete time output samples VOUT at output terminals 18.
The sample stage 12 includes a pair of switches controlled by a clock signal P1 (hereinafter “P1 clock switch(es)”), a pair of switches controlled by a clock signal P2 (hereinafter “P2 clock switch(es)”), a pair of switches controlled by a clock signal PS (hereinafter “PS clock switch(es)”), a capacitor C1, and a capacitor C2. The differential signal VIN is demonstrated in the example of FIG. 1 as a positive rail input signal VIN+, a negative rail input signal VIN−, and a common mode voltage signal CM that is associated with the input signal VIN. The common mode signal CM can have a voltage potential that is substantially centered (i.e., mean) between the signal VIN+ and the signal VIN−. It is to be understood that, because the input signal VIN is a differential signal, the negative rail input signal VIN− is a complement of the positive rail input signal VIN+. Thus, the negative rail input signal VIN− may not be negative relative to zero, but could be negative relative to the common mode signal CM. In addition, the common mode signal CM could have a floating voltage potential, as well. The sample stage 12 also receives another common mode signal CM2, which could be a fixed voltage potential. It is to be understood that the common mode signal CM and the common mode signal CM2 could be the same voltage potential. The hold stage 14 includes a pair of P2 clock switches, a capacitor C3, a capacitor C4, and an inverting amplifier 16. The inverting amplifier 16 has a positive input terminal that is coupled to both the capacitors C1 and C3 and a negative input terminal that is coupled to both the capacitors C2 and C4. The common mode signal CM2 can be a voltage potential that is sufficient to bias the inverting amplifier 16. The inverting amplifier 16 also has output terminals that are coupled to the output terminals 18 of the sample-and-hold circuit 10, which outputs the discrete time output samples VOUT of the input signal VIN.
The PS clock signal defines a sample signal (not shown) that defines a sampling rate associated with the sample-and-hold circuit 10. The sample signal can have a period that defines both a sample phase and a hold phase. An example of the operation of the sample signal in relation to the P1, P2 and PS clock switches is demonstrated in the example of FIG. 2. FIG. 2 illustrates an example of a timing diagram 50 associated with the sample-and-hold circuit 10 in the example of FIG. 1. The timing diagram 50 is demonstrated in the example of FIG. 2 as being an ideal timing diagram. However, it is to be understood that, in actuality, there are delays associated with the timing diagram 50. For example, the example of FIG. 2 demonstrates that the P1 clock switches and the PS clock switches activate and deactivate at substantially the same time. However, it is to be understood that the PS clock switches may actually deactivate before the P1 clock switches to avoid signal dependent charge injection.
In the example of FIG. 2, the sample signal can define the sample phase when the sample signal is asserted (i.e., P1 and PS being logic high) and the hold phase when the sample signal is de-asserted (i.e., P2 being logic low). Accordingly, the P1 and PS clock switches can close during the sample phase, and the P2 clock switches can close during the hold phase. It is to be understood that, throughout the discussion herein of FIG. 2, reference will be made to FIG. 1, such that like identifiers and reference numbers will be used.
During the sample phase, due to the closure of the P1 and PS clock switches, the capacitor C1 is coupled to the signal VIN+ and the common mode signal CM2, and the capacitor C2 is coupled to the signal VIN− and the common mode signal CM2. Therefore, the capacitors C1 and C2 each become charged with a voltage potential of VIN+ and VIN−, respectively, during the sample phase. The timing diagram 50 demonstrates a sample of the input signal VIN being captured at the end (i.e., falling edge) of two separate sample phases, demonstrated in the example of FIG. 2 at the dashed lines 52.
The captured sample of the input signal VIN then gets transferred to the hold stage during each of the subsequent hold phases. For example, during the hold phase, the P1 and PS clock switches open and the P2 clock switches close. The capacitors C1 and C2 become coupled to the common mode voltage CM and the capacitors C3 and C4, respectively. The capacitors C3 and C4 also become coupled to the output terminals 18. The capacitors C1 and C2 therefore discharge the captured sample of the input signal VIN to the capacitors C3 and C4, respectively. During the transition from the sample phase to the hold phase, the capacitors C1, C2, C3, and C4 conserve the total amount of charge between them. Thus, because the capacitors C3 and C4 are also coupled to the common mode signal CM at the input of the inverting amplifier 16 during the hold phase, the input signal VIN at the respective capacitors C3 and C4 experiences a gain that is approximately equal to the ratio of capacitance of the sampling capacitors C1 and C2 to the feedback (i.e., hold) capacitors, and is output at the output terminals 18 as a discrete time output sample VOUT. It is to be understood that, in order to decrease the voltage gain of the sample-and-hold circuit 10, the capacitance value of the capacitors C3 and C4 can be increased linearly or the capacitance value of the capacitors C1 and C2 can be decreased linearly. It is also to be understood that a typical sample-and-hold circuit may set the capacitance of C1 equal to C2, and the capacitance C3 equal to C4.
It is to be understood that the sample-and-hold circuit 10 is not intended to be limited to the example of FIG. 1. For example, the sample-and-hold circuit 10 could have additional common mode voltages associated with the P1, P2 and PS clock switches. Furthermore, the P2 clock switches could merely couple the capacitors C1 and C2 together during the hold phase, instead of coupling each to the common mode signal CM. As another example, another set of P1 clock switches could couple the capacitors C3 and C4 to yet another common mode signal, such that the discrete time output samples VOUT could reflect a level-shifted voltage potential. In addition, the sample-and-hold circuit 10 can also perform single-ended input to differential output conversion, programmable gain, and offset correction functionalities preceding an analog-to-digital converter. Accordingly, the sample-and-hold circuit 10 could be modified in a variety of ways as known in the art.
A potential problem for a typical sample-and-hold architecture is aliasing. For example, noise components having a frequency that is approximately equal to the frequency of a sample signal, or an integer multiple of the frequency of the sample signal, can result in aliasing of the noise components to the baseband signal around approximately 0 Hz at the sampled output. A common solution to the problem of aliasing is filtering the input signal prior to sampling it. For example, a passive RC or LC filter can be implemented to filter the input signal prior to the given sample-and-hold circuit. Simple RC and LC filters are convenient, but often lack efficiency since they attenuate noise efficiently on very high frequencies and hence require the ADC to use a very high sampling frequency. A high order active filter, with multiple-stage amplifiers, can be implemented to filter the input signal prior to the given sample-and-hold circuit with much better attenuation than a passive filter. However, a typical active filter often consumes an undesirably large amount of power. In addition, a typical active filter is larger, thus requiring more die area and making it more difficult to integrate with the sample-and-hold circuit and/or ADC to avoid external noise coupling. They may also degrade the linearity of the signal and introduce phase distortion. Sigma-delta converters are also not very suitable because they cannot handle large analog video input bandwidth requirements.